1. Field of the Invention
The present invention relates to an operation for reading memory cell information in a nonvolatile semiconductor memory device, and more particularly to high-speed sensing technology for the reading operation.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a flash memory, storage of memory cell information is carried out by current driving power of a nonvolatile transistor in the nonvolatile memory cell. That is, the storage of the memory cell information is carried out according to a difference such as whether or not the nonvolatile transistor allows a current to flow with respect to memory cell information of “1”/“0” or whether it supplies a larger amount of current or a smaller amount of current.
Then, sensing of the memory cell information stored in the nonvolatile semiconductor memory device is carried out depending on whether or not a current flows through a digit line connected to a selected memory cell, or the size relationship between the flowing current and a reference current flowing to a reference cell.
FIG. 22 shows an entire block diagram of a nonvolatile semiconductor memory device of a conventional art. Memory cells MC are disposed in a matrix form so as to form a memory core portion A100. The memory cells are grouped by a predetermined quantity as a basic unit so that sector SEC100m and SEC100n are formed. By decoding an address signal Add by means of a decoder 101 when reading memory cell information, a word line WL belonging to a selected sector is activated and then, the memory cell MC is connected to a global bit line GBL, so that appropriate memory cell information appears in the global bit line GBL.
In the memory core portion A100 (FIG. 23), bit lines LBL00 through LBL03 and LBL10 through LBL13 of each sector are disposed independently because of necessity of separate operations of the sector SEC100 and sector SEC101. That is, there is a hierarchical structure composed of global bit lines GBL0 and GBL1 passing through the sectors and the two local bit lines LBL00 through LBL03 and LBL10 through LBL13 connected to the global bit line through a sector switch. A plurality of the memory cells MC disposed in a sector are connected to each local bit line. FIG. 23 exemplifies memory cell groups MC00 through MC03 selected by a word line WL0 in the sector SEC100 and memory cell groups MC100 through MC13 selected by a word line WL1 in the sector SEC101.
When reading memory cell information, any one sector is selected so that an appropriate word line (WL0 or WL1) is activated. Consequently, all the local bit lines LBL00 through LBL03 in the selector or LBL10 through LBL13 in the sector are connected to the respective memory cells MC00 through MC03 or MC10 through MC13, so that memory cell information appears. Then, any one of two sector switches connected to the global bit lines GBL0, GBL1 is selected and the respective global bit lines GBL0, GBL1 are connected to the memory cells MC00 through MC03 or MC10 through MC13 through a sector switch. Upon reading memory cell information, all the global bit lines GBL (FIG. 22) possess selected memory cell information. Meanwhile, redundant configurations SP100, SP101 of the memory core portion A100 are constructed with the global bit line SGBL as a basic unit.
Returning to FIG. 22, every predetermined number of the global bit lines GBL connected to the memory cells MC is inputted to a column selecting portion B100 and any one is selected from them and connected to a data bus LDB. FIG. 24 shows an example of a circuit in which one is selected from 32 global bit lines GBL0 through GBL31 and connected to the data bus line LDB. One signal of decoding signals YD00 through YD1F is activated according to an address signal Add. Consequently, only a path gate transistor connected to an activated decoding signal turns on, so that an appropriate global bit line is connected to a data bus line LDBn and memory cell information appears in the data bus LDB.
The memory cell information appearing in the data bus line LDB is detected by comparing a current flowing from the data bus line LDB to the memory cell MC depending on current driving performance of the memory cell MC as described above with a reference current. More specifically, after current is converted to voltage, this comparison is carried out by a differential amplifier 106. Cascode portions 104, 105 execute current/voltage conversion. FIG. 25 shows an example of a concrete circuit. When a current flowing to the data bus line LDB and the reference current flow through NMOS transistors QN102, QN202, input voltage to the differential amplifier 106 is adjusted depending on current.
Here, the data bus line LDB is constructed with multiple bits such as 8 bits, 16 bits and the above-described reading structure is provided on each data bus line LDB. That is, as for the cascode circuit 104 and the differential amplifier 106, 8 sets thereof are provided for 8-bit configuration and 16 sets are provided for 16-bit configuration. Circuits corresponding to a constructed multiple bit configuration are necessary. Meanwhile, there is a reference cell RC100 and there is also a cascode portion 105 on the reference current side corresponding to the reference cell. This output is connected to respective differential amplifiers in common. Therefore, parasitic capacitance between input signal lines on memory cell information side and reference side in each differential amplifier 106 is unbalanced. To adjust this, generally, a capacitance load CLD2 is applied to an input signal line on the memory cell information side.
Further, the reference cell RC100 is provided in a different dedicated region from a sector region in the memory core portion A100 in order to avoid influences of a programming operation to the memory cell MC and voltage stress by an erase operation. Thus, a reference bus line RB to which the reference cell RC100 in a dedicated region is connected is not connected to other memory cells on a path but connected directly to the cascode portion 105. On the other hand, a plurality of non-selected memory cells are connected to the local bit line to which the memory cell MC is connected, so as to be connected to the global bit line GBL through the sector switch, thereby constructing a hierarchical structure. Therefore, in a path leading from the memory cell MC to the cascode portion 104, there exist a junction capacitance of a transistor in a non-selected memory cell MC, a parasitic capacitance such as an interline capacitance between the local bit line and global bit line and another bit line and word line disposed adjacent to or on an upper/lower layer or other signal line or the like and a parasitic resistance due to a sector switch or the like. To adjust an unbalanced condition of the parasitic element, generally, a capacitance load CLD1 is added to a path leading from the reference cell RC100 to the cascode portion 105. Although FIG. 22 shows a case where the reference cell RC100 is disposed within the memory core portion A100, the present invention is not restricted to this example, such that it may be disposed outside of the memory core portion A100.
By adjusting the parasitic element component with the capacitance loads CLD1, CLD2, transient response characteristics on the memory cell information side and reference side are equalized so as to enable sensing in a transient state without waiting for a signal propagation delay due to the parasitic element, thereby reducing sensing time.
The data bus line LDB is used for writing memory cell information (hereinafter referred to as a program). That is, input data IDAT amplified by a write amplifier 103 is outputted to the data bus line LDB. By selecting an appropriate global bit line GBL by means of column selecting means B100, program action is executed in the memory cell MC by the global bit line GBL through the local bit line.
In a conventional nonvolatile semiconductor memory device 100, a parasitic capacitance in a current path on the memory cell information side leading from the memory cell MC to the cascode portion 104 is matched artificially by adding the capacitance load CLD1 to the current path on the reference cell side.
However, the parasitic capacitance on the memory cell information side varies with a distribution having a certain width because of a tolerable variation in the manufacturing process. That is, an interval between adjoining lines varies due to a variation in the etching processing of each line and interline capacitance between the adjoining lines varies over a certain width. Further, due to variation of the thickness of a layer insulating film, a gap between lines of the upper and lower layers varies, so that the interline capacitance between the adjoining lines varies over a certain width. Further, the junction capacitance and on resistance also vary over each a certain width due to variation in various kinds of parameters of the transistor such as gate oxide film, concentration and depth of diffused layer and the like.
Accompanied by an increased capacity of the nonvolatile semiconductor memory device and an increased size of its chip die, a difference of the parasitic capacitance in a chip face tends to increase even within the same chip. The diameter of the wafer has been increased at the same time, and thus there is a fear that the difference in the wafer face may also increase.
That is, a surrounding environment in which bit lines are disposed and physical parameters of a formed path are different between a current path leading from a memory cell MC disposed in a sector through a bit line having a hierarchical structure and a reference current path directly connected from a reference cell disposed in its dedicated region. Thus, even if the capacitance loads CLD1, CLD2 including the characteristics of both the parasitic element components are applied at the design stage, it is difficult to match the characteristic of the reference side with the characteristic of the parasitic element component, including these variable factors, because manufacturing variation and trend of difference in chip or wafer face distribution are different from one and another.
Therefore, in a transient stage during a reading operation, accompanying a propagation delay of a signal due to the parasitic element component, potential changes in current paths on the memory cell information side and the reference side will not match. Therefore, in order to detect memory cell information, it is necessary to wait until a potential change converges in a specified range, thereby obstructing a reading operation from being carried out rapidly, which is a problem which should be solved.